EH59 Series Oscillator

Quartz Crystal Clock Oscillators XO (SPXO) LVCMOS (CMOS) 1.8Vdc 4 Pad 2.0mm x 2.5mm Ceramic Surface Mount (SMD)
Revision  G  09/27/2011

Electrical Specifications

Nominal Frequency 2.600MHz to 133.000MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25°C, Shock, and Vibration)
±100ppm Maximum
±50ppm Maximum
±25ppm Maximum
±20ppm Maximum
Operating Temperature Range 0°C to +70°C
-40°C to +85°C
Supply Voltage (VDD) 1.8VDC ±5%
Input Current No Load
3.5mA Maximum over Nominal Frequency of 2.600MHz to 25.000MHz
4mA Maximum over Nominal Frequency of 25.000001MHz to 75.000MHz
5mA Maximum over Nominal Frequency of 75.000001MHz to 100.000MHz
8mA Maximum over Nominal Frequency of 100.000001MHz to 133.000MHz
Output Voltage Logic High (VOH) 90% of VDD Minimum (IOH= -8mA)
Output Voltage Logic Low (VOL) 10% of VDD Maximum (IOL= +8mA)
Duty Cycle Measured at 50% of waveform
50 ±10(%)
50 ±5(%) (Only available over Nominal Frequency range of 2.600MHz to 50.000MHz)
Rise Time/Fall Time Measured at 20% to 80% of Waveform
6nSec Maximum from 2.600MHz to 50.000MHz
4nSec Maximum from 50.000001MHz to 75.000MHz
2nSec Maximum from 75.000001MHz to 133.000MHz
Load Drive Capability 15pF Maximum
Aging (at 25°C) ±5ppm/year Maximum
Storage Temperature -55°C to +125°C
Output Control Function Tri-State Enable High
Tri-State Input Voltage 90% of VDD Minimum or No Connection to enable output.
10% of VDD Maximum disable output(High Impedance).
Standby Current 10µA Maximum (Pin 1 = Ground)
RMS Phase Jitter Fj=12kHz to 20MHz
20pSec Typical, 30pSec Maximum
Period Jitter (RMS) 15pSec Typical
Period Jitter (pk-pk) 100pSec Typical, 200pSec Maximum
Start Up Time 10mSec Maximum